The subject matter disclosed herein relates to enhancing strain in an integrated circuit. Specifically, the subject matter disclosed herein relates to a structure and method for enhancing strain in an integrated circuit by using a localized implant into a gate region prior to gate etch.
The application of stresses to field effect transistors (FETs) is known to improve their performance. When applied in a longitudinal direction (i.e., in the direction of current flow), tensile stress is known to enhance electron mobility (or n-channel FET (NFET) drive currents) while compressive stress is known to enhance hole mobility (or p-channel FET (PFET) drive currents). Typical methods for enhancing stress in an integrated circuit involve the use of a blanket implantation across an entire semiconductor substrate. For example, as shown in FIG. 1, semiconductor substrate 100 is provided, including a region defining a gate region 102. A thin gate layer 104 is then deposited across substrate 100. Substrate 100 is then blanket implanted, i.e., implanted across the entire surface of substrate 100, as illustrated by arrows 106. A thicker gate layer 108 (FIG. 2) is then deposited across substrate 100 and finally substrate 100 is annealed to create the desired stress.